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| S3C7031/7032 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW OVER VIEW The S3C7031/7032 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core. With comparator inputs, high-current LED direct-drive pins, serial I/O interface, and a versatile 8-bit timer/counter, the S3C7031/7032 offers an excellent design solution for a wide range of applications such as mouse controllers, subsystem controllers, and toys. Up to 15 pins of the 20-pin DIP or 20-pin SOP package can be dedicated to I/O. Pull-up resistors are assignable to all of the pins by software. Four vectored interrupts provide fast response to internal and external events. In addition, the S3C7031/7032's advanced CMOS technology provides for very low power consumption and a wide operating voltage range. DEVELOPMENT SUPPORT The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based development environment for KS57-series microcontrollers that is powerful, reliable, and portable. In addition to its easy to use window-oriented program development structure, the SMDS toolset includes versatile debugging, trace, instruction timing, and performance measurement applications. The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard object files that also contain program control data for SMDS compatibility. 1-1 PRODUCT OVERVIEW S3C7031/7032 FEATURES Memory -- 1024 x 8-bit program memory (S3C7031) (ROM) -- 2048 x 8-bit program memory (S3C7032) (ROM) -- 128 x 4-bit data memory (S3C7031) (RAM) -- 256 x 4-bit data memory (S3C7032) (RAM) I/O Pins -- Up to 15 pins for 20-DIP and 20-SOP package Comparator Inputs -- 4-channel mode Internal reference: 4-bit resolution -- 3-channel mode External reference 8-Bit Basic Timer -- Programmable interval timer 8-Bit Timer/Counter -- Programmable interval timer -- External event counter function -- Timer clock output to TIO pin Watch Timer -- Time interval generation: 0.5 s, 3.9 ms at 4.19 MHz -- Four frequency outputs to BUZ pin Bit Sequential Carrier -- 16-bit serial data transfer in arbitrary format 8-Bit Serial I/O Interface -- 8-bit transmit/receive mode -- 8-bit receive-only mode -- LSB-first or MSB-first transmission selectable -- Internal or external clock source Interrupts -- One external interrupt vector -- Three internal interrupt vectors -- Two quasi-interrupts Memory-Mapped I/O Structure Two Power-Down Modes -- Idle mode: Only the CPU clock stops -- Stop mode: Main system clock stops On-Chip Crystal, Ceramic, Or RC Oscillator -- Crystal/ceramic: 4.19 MHz (typical) -- RC: 1 MHz (typical) -- CPU clock divider circuit (by 4, 8, or 64) Frequency Outputs -- Eight frequency outputs to the CLO pin Instruction Execution Times -- 0.95, 1.91, 15.3 s at 4.19 MHz (5 V), 4 s at 1 MHz (2.7 V) Operating Temperature: -- - 40C to 85C Operating Voltage Range: -- 2.7 V to 6.0 V Package Type: -- 20-DIP, 20-SOP 1-2 S3C7031/7032 PRODUCT OVERVIEW BLOCK DIAGRAM RESET Basic Timer Interrupt Control Block Watch Timer Internal Interrupts P2.0 - P2.3 P3.0/SCK P3.1/SO P3.2/SI P3.3/BUZ I/O Port 2 XIN XOUT I/O Port 0 P0.0/CLO P0.1/TIO P0.2/INT1 Clock Stack Pointer Program Counter 8-Bit Timer/ Counter Instruction Decoder I/O Port 3 Arithmetic and Logic Unit Serial I/O Port Program Status Word Comparator Flags I/O Port 1 P0.0/KS0/CIN0 P0.1/KS1/CIN1 P0.2/KS2/CIN2 P0.3/KS3/CIN3 Data Memory (2) Program Memory (1) NOTES: 1. Program Memory is 1-KByte (S3C7031) and 2-KByte (S3C7032). 2. Data Memory is 128 x 4bit (S3C7031) and 256 x 4bit (S3C7032). Figure 1-1. S3C7031/7032 Block Diagram 1-3 PRODUCT OVERVIEW S3C7031/7032 PIN ASSIGNMENTS P0.0/CLO P0.1/TIO P0.2/INT1 P0.0/KS0/CIN0 P0.1/KS1/CIN1 P0.2/KS2/CIN2 P0.3/KS3/CIN3 XOUT XIN VSS 1 2 3 4 5 6 7 8 9 10 KS57C7031/ KS57C7032 (Top view) 20 19 18 17 16 15 14 13 12 11 VDD P3.3/BUZ P3.2/SI P3.1/SO P3.0/SCK P2.3 P2.2 P2.1 P2.0 RESET NOTE: Pin assignments are identical for the 20-pin DIP and SOP package. Figure 1-2. S3C7031/7032 Pin Assignment Diagram (20-pin DIP/SOP Package) PIN DESCRIPTIONS Table 1-1. S3C7031/7032 Pin Descriptions Pin Name P0.0 P0.1 P0.2 Pin Type I/O Description 3-bit I/O port. 1-bit or 3-bit read/write and test is possible. Pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. Pins are individually configurable as input or output. Same as port 0 except that port 1 is a 4-bit I/O port. Number 1 2 3 Share Pin CLO TIO INT1 P1.0 P1.1 P1.2 P1.3 I/O 4 5 6 7 KS0/CIN0 KS1/CIN1 KS2/CIN2 KS3/CIN3 1-4 S3C7031/7032 PRODUCT OVERVIEW Table 1-1. S3C7031/7032 Pin Descriptions (Continued) Pin Name P2.0-P2.3 P3.0 P3.1 P3.2 P3.3 Pin Type I/O Description 4-bit I/O port. 1-bit, 4-bit or 8-bit read/write and test is possible. Pins are individually configurable as input or output. Pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. Ports are software configurable as n-channel open-drain outputs or push-pull output by software. Ports 2 and 3 can be paired to enable 8-bit data transfer. Eight frequency outputs External clock input or timer clock output External interrupts with rising or falling edge detection Quasi-interrupts with falling edge detection 4-channel comparator input. CIN0-CIN2: comparator input only. CIN3: comparator input or external reference input Serial interface clock signal Serial data output Serial data input 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at 4.19 MHz for buzzer sound Crystal, ceramic, or RC signal for system clock Reset signal Power supply Ground Number 12-15 16 17 18 19 Share Pin -SCK SO SI BUZ CLO TIO INT1 KS0-KS3 CIN0-CIN3 I/O I/O I/O I/O I/O 1 2 3 4-7 4-7 P0.0 P0.1 P0.2 P1.0-P1.3 P1.0-P1.3 SCK SO SI BUZ XIN, XOUT RESET VDD VSS I/O I/O I/O I/O -I --- 16 17 18 19 9, 8 11 20 10 P3.0 P3.1 P3.2 P3.3 ----- Table 1-2. Overview of S3C7031/7032 Pin Data Pin Numbers 1-3 4-7 12-5 16-19 11 20, 10 9, 8 Pin Names P0.0-P0.2 P1.0-P1.3 P2.0-P2.3 P3.0-P3.3 RESET VDD, VSS XIN, XOUT Share Pins CLO, TIO, INT1 KS0/CIN0-KS3/CIN3 - I/O Type I/O I/O I/O I/O I --- Reset Value Input Input Input Input ---- Circuit Type 2 4 3 3 1 --- SCK, SO, SI, BUZ ---- 1-5 PRODUCT OVERVIEW S3C7031/7032 PIN CIRCUIT DIAGRAMS In Schmitt Trigger Figure 1-3. Pin Circuit Type 1 VDD Pull-up Registor Pull-up Enable Typical 50 K (VDD = 5V) VDD Data I/O Output DIsable VSS Schmit Trigger Figure 1-4. Pin Circuit Type 2 1-6 S3C7031/7032 PRODUCT OVERVIEW VDD Pull-up Registor Pull-up Enable Typical 50 K (VDD =5V) VDD Data Open-drain I/O Output Disable VSS Schmit Trigger Figure 1-5. Pin Circuit Type 3 1-7 PRODUCT OVERVIEW S3C7031/7032 VDD Pull-up Registor Pull-up Enable Typical 50 K (VDD =5V) P-CH VDD Data Open-drain I/O Output Disable VSS Schmit Trigger (Digital) In Intk (Quasi) REF (P1.3 Only) In (Analog) + Comparator REF Digital or Analog Selectable by Software Figure 1-6. Pin Circuit Type 4 1-8 S3C7031/7032 ELECTRICAL DATA 14 OVERVIEW -- I/O capacitance ELECTRICAL DATA In this section, information on S3C7031/7032 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Oscillators characteristics -- Comparator electrical characteristics -- A.C. electrical characteristics -- Operating voltage range Oscillation Characteristics -- System clock oscillator frequencies and stabilization time Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request 14-1 ELECTRICAL DATA S3C7031/7032 Miscellaneous Timing Waveforms -- Clock timing measurement at XIN -- TIO timing -- Input timing for RESET -- Input timing for external interrupts and quasi-interrupts -- Serial data transfer timing Characteristic Curves -- IDD vs Frequency -- IDD vs VDD -- IOL vs VOL (P0.0) -- IOL vs VOL (P1.1) -- IOL vs VOL (P2.0) -- IOH vs VOH (P0.0) -- IOH vs VOH (P1.1) 14-2 S3C7031/7032 ELECTRICAL DATA Table 14-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL TA Tstg All I/O ports - One I/O port active All I/O ports active Output Current Low One I/O port active All I/O port, total Operating Temperature Storage Temperature - - Conditions - Rating - 0.3 to + 7.0 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 -5 - 15 25 100 - 40 to + 85 - 65 to + 150 C C Units V V V mA mA Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.7 V to 6.0 V) Parameter Input High Voltage Symbol VIH1 VIH2 Input Low Voltage VIL1 VIL2 Output High Voltage VOH1 Conditions Ports 0, 1, 2, 3, RESET XIN, XOUT Ports 0, 1, 2, 3, RESET XIN, XOUT VDD = 4.5 V to 6.0 V IOH = - 3 mA Ports 0, 1, 2, 3 except P0.0 VDD = 4.5 V to 6.0 V IOH = - 6 mA Ports 0, 1, 2, 3 except P0.0 VOH2 VDD = 4.5 V to 6.0 V IOH = - 10 mA P0.0 VDD = 4.5 V to 6.0 V IOL = 25 mA Ports 0, 1, 2, 3 except P0.0 VDD = 4.5 V to 6.0 V IOL = 50 mA P0.0 VDD - 1.0 VDD - 0.4 Min 0.7 VDD VDD - 0.5 - Typ - - - Max VDD VDD 0.3 VDD 0.4 - V V Units V VDD - 2.0 VDD - 0.9 - VDD - 2.0 - - Output Low Voltage VOL1 - 1.4 2.0 V VOL2 - 1.6 2.0 V 14-3 ELECTRICAL DATA S3C7031/7032 Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.7 V to 6.0 V) Parameter Input High Leakage Current Symbol ILIH1 Conditions VIN = VDD All input pins except ILIH2 VIN = VDD XIN, XOUT VIN = 0 V All input pins except ILIL2 VIN = 0 V XIN, XOUT VO = VDD All output pins VO = 0 V All output pins VIN = 0 V; VDD = 5 V - 10 % Ports 0, 1, 2, 3 VIN = 0 V; VDD = 3 V - 10 % Ports 0, 1, 2, 3 VDD = 5 V 10 % (2) 4.19 MHz crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10 % (3) 4.19 MHz crystal oscillator C1 = C2 = 22 pF Idle mode; VDD = 5 V 10 % 4.19 MHz crystal oscillator C1 = C2 = 22 pF Idle mode; VDD = 3 V 10 % 4.19 MHz crystal oscillator C1 = C2 = 22 pF Stop mode VDD = 5 V - 10 % Stop mode VDD = 3 V - 10 % - - Min - Typ - Max 3 Units A ILIH2 Input Low Leakage Current ILIL1 15 - 20 -3 A ILIL2 Output High Leakage Current Output Low Leakage Current Pull- Up Resistor ILOH -15 - - 20 3 A ILOL - - -3 A RL 15 30 - 50 100 1.7 80 200 8.0 K Supply Current (2) IDD1 mA 0.6 1.2 IDD2 - 0.5 1.8 mA 0.2 1.0 IDD3 0.2 0.1 5 3 A NOTES: 1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up resistors. 2. 3. For high-speed controller operation, set the PCON register to 0011B. For low-speed controller operation, set the PCON register to 0000B. 14-4 S3C7031/7032 ELECTRICAL DATA Table 14-3. Oscillators Characteristics (TA = - 40 C to + 85 C, VDD = 5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT Parameter Oscillation frequency(1) Test Condition - Min 0.4 Typ - Max 4.5 Units MHz C1 C2 Stabilization time (2) After VDD reaches the minimum level of its variable range - - - 4 ms Crystal Oscillator Oscillation frequency(1) XIN XOUT 0.4 4.19 4.5 MHz C1 C2 Stabilization time (2) VDD = 2.7 V to 4.5 V VDD = 4.5 V to 6.0 V - - 0.4 - - - 30 10 4.5 ms External Clock XIN XOUT XIN input frequency (1) - MHz XIN input high and low level width (tXH, tXL) RC Oscillator Frequency XIN R XOUT - VDD = 5 V 111 0.6 - 1 1250 2.3 ns MHz VDD = 3 V 0.4 0.8 1.5 NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 14-5 ELECTRICAL DATA S3C7031/7032 Table 14-4. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF Table 14-5. Comparator Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.0 V to 6.0 V) Parameter Input Voltage Range Reference Voltage Range Input Voltage Accuracy Internal Reference External Reference Input Leakage Current Symbol - VREF Condition - - - Min 0 0 - Typ - - - Max VDD VDD - 150 Units V V mV VCIN1 VCIN2 ICIN, IREF - - - -3 - - - 50 3 A 14-6 S3C7031/7032 ELECTRICAL DATA Table 14-6. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.7 V to 6.0 V) Parameter Instruction Cycle Time Symbol tCY f TI tTIH, tTIL Conditions VDD = 4.5 V to 6.0 V VDD = 2.7 V to 4.5 V TIO Input Frequency VDD = 4.5 V to 6.0 V VDD = 2.7 V to 4.5 V TIO Input High, Low Width SCK Cycle Time VDD = 4.5 V to 6.0 V VDD = 2.7 V to 4.5 V tKCY VDD = 4.5 V to 6.0 V; Input VDD = 4.5 V to 6.0 V; Output VDD = 2.7 V to 4.5 V; Input VDD = 2.7 V to 4.5 V; Output SCK High, Low Width tKH, tKL VDD = 4.5 V to 6.0 V; Input 0.48 1.8 800 950 3200 3800 400 - - ns - - ns - Min 0.95 3.8 0 - 1 275 - MHz kHz s Typ - Max 64 Units s VDD = 4.5 V to 6.0 V; Output tKCY/2-50 VDD = 2.7 V to 4.5 V; Input 1600 VDD = 2.7 V to 4.5 V; Output tKCY/2-50 SI Setup Time to SCK High SI Hold Time to SCK High Output Delay for SCK to SO tSIK Input Output tKSI Input Output tKSO VDD = 4.5 V to 6.0 V; Input VDD = 4.5 V to 6.0 V; Output VDD = 2.7 V to 4.5 V; Input VDD = 2.7 V to 4.5 V; Output Interrupt Input High, Low Width RESET Input Low Width tINTH, tINTL tRSL INT1, KS0-KS3 Input 10 10 - - 100 150 400 400 - - 300 250 1000 1000 - - s s ns - - ns - - ns 14-7 ELECTRICAL DATA S3C7031/7032 CPU Clock 1.0475MHz 1.00MHz 750kHz 500kHz 250kHz 15.6kHz 1 2 3 4 5 6 7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64) Figure 14-1. Standard Operating Voltage Range Table 14-7. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data Retention Supply voltage Data Retention Supply Current Release Signal Set Time Oscillation Stabilization Wait Time (1) Symbol VDDDR IDDDR tSREL tWAIT Condition - VDDDR = 2.0 V - Released by RESET Released by interrupt Min 2.0 - 0 - - Typ -- 0.1 -- 217 / fx (2) Max 6.0 10 - - - Units V A s ms NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 14-8 S3C7031/7032 ELECTRICAL DATA TIMING WAVEFORMS Internal RESET Operation Stop Mode Data Retention Mode ~ ~ ~ ~ Idle Mode Operating Mode VDD RESET Execution Of Stop Instrction VDDDR tSREL tWAIT Figure 14-2.Stop Mode Release Timing When Initiated By RESET Idle Mode Stop Mode Data Retention Mode VDDDR tSREL Normal Mode ~ ~ ~ ~ VDD Execution Of Stop Instrction Power - Down Mode Terminating Signal (Interrupt Request) tWAIT Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request 14-9 ELECTRICAL DATA S3C7031/7032 0.7 VDD Measurement Points 0.3 VDD 0.7 VDD 0.3 VDD Figure 14-4. A.C. Timing Measure Points (Except for XIN) 1/fx tXL tXH XIN VDD - 0.5V 0.4 V Figure 14-5. Clock Timing Measurement at XIN 1/fTCL tTIL tTIH TIO 0.7 VDD 0.3 VDD Figure 14-6. TIO Timing 14-10 S3C7031/7032 ELECTRICAL DATA tRSL RESET 0.3 VDD Figure 14-7. Input Timing for RESET Signal tINTL tINTH INT1 KS0 to KS3 0.7 VDD 0.3 VDD Figure 14-8. Input Timing for External Interrupts 14-11 ELECTRICAL DATA S3C7031/7032 tKCY tKL SCK tKH 0.7 VDD 0.3 VDD tKSO tKIS 0.7 VDD SI Input Data 0.3 VDD tKSO SO Output Data Figure 14-9. Serial Data Transfer Timing 14-12 S3C7031/7032 ELECTRICAL DATA CHARACTERISTIC CURVES NOTE The characteristic values shown in the following graphs are based on actual test measurements. They do not, however, represent guaranteed operating values. 70 63 54 49 IOL (mA) 42 35 28 21 14 7 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 VDD = 4.5V VDD = 6.0V VOL (V) Figure 14-10. IOL vs. VOL (Port 0,1,2,3) 14-13 ELECTRICAL DATA S3C7031/7032 100 90 80 70 IOL (mA) 60 50 40 30 20 10 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 VDD = 4.5V VDD = 6.0V VOL (V) Figure 14-11. IOL vs. VOL (Port 0.0) -30.0 -27.0 -24.0 -21.0 IOL (mA) -18.0 -15.0 -12.0 -9.0 -6.0 -3.0 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 VDD = 4.5V VDD = 6.0V VOL (V) Figure 14-12. IOH vs. VOH (Port 0,1,2,3except P0.0) 14-14 S3C7031/7032 ELECTRICAL DATA 3.0 2.5 2 IDD (mA) IDD1 (/4) 1.5 1 0.5 IDD2 ~ ~ 0 3.0 4.0 VDD (V) 5.0 6.0 0 Figure 14-13. IDD vs. VDD 2.5 2 IDD1(mA) 1.5 1 0.5 0 VDD = 5.5V(/4) 0 1.0 2.0 fx (MHz) 3.0 4.0 5.0 Figure 14-14. IDD vs. Frequency 14-15 S3C7031/7032 MECHANICAL DATA 15 #20 6.40 0.20 MECHANICAL DATA This section contains the following information about the device package: -- A 20-pin DIP package is available for S3C7031/7032. -- A 20-pin SOP package is available for S3C7031/7032. #11 7.62 20-DIP-300A #1 #10 5.08 MAX 3.52 0.20 0-15 0.25 + 0.10 - 0.05 26.40 (1.77) 0.20 0.51 MIN 0.46 0.10 1.52 0.10 2.54 NOTE: Dimensions are in millimeters Figure 15-1. 20-pin DIP-300A Package Dimensions 3.30 0.30 15-1 MECHANICAL DATA S3C7031/7032 #20 #11 7.50 0.20 10.30 0.30 20-SOP-375 0.203 + 0.10 - 0.05 9.53 #1 12.74 0.20 (0.66) #10 2.30 0.10 0.85 0.20 0-8 2.50 MAX 0.40 + 0.10 - 0.05 1.27 NOTE: Dimensions are in millimeters Figure 15-2. 20-pin SOP-375 Package Dimensions 15-2 0.05 MIN |
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